Cypress Semiconductor /psoc63 /PASS /AREF /AREF_CTRL

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Interpret as AREF_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NORMAL)AREF_MODE 0AREF_BIAS_SCALE 0AREF_RMB 0 (CTB_IPTAT_SCALE)CTB_IPTAT_SCALE 0CTB_IPTAT_REDIRECT 0 (SRSS)IZTAT_SEL 0 (CLOCK_PUMP_PERI_SEL)CLOCK_PUMP_PERI_SEL 0 (SRSS)VREF_SEL 0 (OFF)DEEPSLEEP_MODE 0 (DEEPSLEEP_ON)DEEPSLEEP_ON 0 (ENABLED)ENABLED

DEEPSLEEP_MODE=OFF, VREF_SEL=SRSS, IZTAT_SEL=SRSS, AREF_MODE=NORMAL

Description

global AREF control

Fields

AREF_MODE

Control bit to trade off AREF settling and noise performance

0 (NORMAL): Nominal noise normal startup mode (meets normal mode settling and noise specifications)

1 (FAST_START): High noise fast startup mode (meets fast mode settling and noise specifications)

AREF_BIAS_SCALE

BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) 0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) 1: 250nA (‘default’ setting to meet bandgap performance (noise/startup) and IDDA specifications) 2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) 3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times)

AREF_RMB

AREF control signals (RMB).

Bit 0: Manual VBG startup circuit enable 0: normal VBG startup circuit operation 1: VBG startup circuit is forced ‘always on’

Bit 1: Manual disable of IPTAT2 DAC 0: normal IPTAT2 DAC operation 1: PTAT2 DAC is disabled while VBG startup is active

Bit 2: Manual enable of VBG offset correction DAC 0: normal VBG offset correction DAC operation 1: VBG offset correction DAC is enabled while VBG startup is active

CTB_IPTAT_SCALE

CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). 0: 1uA 1: 100nA

CTB_IPTAT_REDIRECT

Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). 0: Opamp.IPTAT = AREF.IPTAT and Opamp.IZTAT= AREF.IZTAT 1: Opamp.IPTAT = HiZ and Opamp.IZTAT= AREF.IPTAT

*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp.IZTAT/IPTAT will be HiZ.

IZTAT_SEL

iztat current select control

0 (SRSS): Use 250nA IZTAT from SRSS

1 (LOCAL): Use locally generated 250nA

CLOCK_PUMP_PERI_SEL

CTBm charge pump clock source select. This field has nothing to do with the AREF. 0: Use the dedicated pump clock from SRSS (default) 1: Use one of the CLK_PERI dividers

VREF_SEL

bandgap voltage select control

0 (SRSS): Use 0.8V Vref from SRSS

1 (LOCAL): Use locally generated Vref

2 (EXTERNAL): Use externally supplied Vref (aref_ext_vref)

DEEPSLEEP_MODE

AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)

0 (OFF): All blocks ‘OFF’ in DeepSleep

1 (IPTAT): IPTAT bias generator ‘ON’ in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)

2 (IPTAT_IZTAT): IPTAT bias generator and outputs ‘ON’ in DeepSleep (used for biasing the CTBm with a PTAT current only in deepsleep)

*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep

3 (IPTAT_IZTAT_VREF): IPTAT, VREF, and IZTAT generators ‘ON’ in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode.

DEEPSLEEP_ON
  • 0: AREF IP disabled/off during DeepSleep power mode
  • 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)
ENABLED

Disable AREF

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